`include "defines.v"
module ysyx_210448_pause (
    input clk,
    input wire rst,
    input wire wb_ok,
    input wire id_fetched,
    input wire if_fetched,
    input wire ena1,
    input wire ena2,
    input wire [63:0] regs_o[0 : 31],
    input wire [63:0] exe_data,
    input wire [63:0] mem_data,
    input wire [63:0] wb_data,
    input wire [6:0] mem_opcode,
    input wire [6:0] exe_opcode,
    input reg [4:0] id_rs1,
    input reg [4:0] id_rs2,
    output reg id_ena1,
    output reg id_ena2,
    input reg [4:0] exe_rd,
    input reg [4:0] mem_rd,
    output reg [63:0] p_exe_op1,
    output reg [63:0] p_exe_op2,
    output reg p_ready1,
    output reg p_ready2,
    output wire ld
);
//wire ld;
assign ld=((mem_opcode==7'b0000011)||(exe_opcode==7'b0000011))?1:0;
always @(posedge clk) begin
    if(rst==1'b1)
    begin 
        p_exe_op1<=64'b0;
        p_ready1<=1'b0;
    end
    else if((~ld)&&(id_fetched))
    begin
        if((id_rs1==mem_rd)&&(id_rs1!=0)&&(mem_rd!=0)&&(mem_opcode!=7'b0000011)) 
        begin//隔一条指令
            p_exe_op1<=wb_data;
            p_ready1<=1'b1;
        end
        else if((id_rs1==exe_rd)&&(id_rs1!=0)&&(exe_rd!=0)&&(exe_opcode!=7'b0000011))
        begin  //相邻指令
            p_exe_op1<=mem_data;
            p_ready1<=1'b1;
        end
    end
    else if(if_fetched)
    begin
        p_exe_op1<=64'b0;
        p_ready1<=1'b0;
    end
   
end
always @(posedge clk) begin
    if(rst==1'b1)
    begin 
        p_exe_op2<=64'b0;
        p_ready2<=1'b0;
    end
    else if((~ld)&&(id_fetched))
    begin
        if((id_rs2==mem_rd)&&(id_rs2!=0)&&(mem_rd!=0)&&(mem_opcode!=7'b0000011))
        begin  //隔一条指令
            p_exe_op2<=wb_data;
            p_ready2<=1'b1;
        end
        else if((id_rs2==exe_rd)&&(id_rs2!=0)&&(exe_rd!=0)&&(exe_opcode!=7'b0000011))  
        begin//相邻指令
            p_exe_op2<=mem_data;
            p_ready2<=1'b1;
        end
    end
    else if(if_fetched)
    begin
        p_exe_op2<=64'b0;
        p_ready2<=1'b0;
    end
end



endmodule

